PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING
This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow).
Committee(s): JC-14.1
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STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
Committee(s): JC-14, JC-14.3
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GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE
This document gathers and organizes common standards and publications relating to quality processes and methods relating to the solid-state, microelectronics, and associated industries. This is intended to facilitate access to the applicable documents when working with electronic hardware. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts.
Committee(s): JC-14.4
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EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES
The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification.
Committee(s): JC-14, JC-14.1
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FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)
This document describes package-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.
Committee(s): JC-14.2
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Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices.
Committee(s): JC-14, JC-14.3
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HIGH TEMPERATURE STORAGE LIFE
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any).
Committee(s): JC-14.1
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JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)
The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations.
Committee(s): JC-14, JC-14.1
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MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999.
Status: Rescinded, May 2000J-STD-020 is now on revision F.
Committee(s): JC-14, JC-14.1
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Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature
This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation.
Committee(s): JC-14, JC-14.1
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ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES
This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical and
reliability testing. These tests are used frequently in qualifying integrated circuits as a new
product, a product family, or as products in a process which is being changed.
Committee(s): JC-14.3
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RELIABILITY QUALIFICATION OF POWER AMPLIFIER MODULES
This standard is intended to identify a core set of qualification tests that apply specifically for Power Amplifier Modules and their primary application in mobile devices such as cellular phones. This standard is intended to describe specific stresses and failure mechanisms that are specific to compound semiconductors and power amplifier modules. It is intended to establish more meaningful and efficient qualification testing.
Committee(s): JC-14.7
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FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc.
Committee(s): JC-14.2
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Information Requirements for the Qualification of Solid State Devices
This standard defines the requirements for the device qualification package, which the supplier provides to the customer.
Committee(s): JC-14, JC-14.3
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GUIDELINES FOR THE PACKING, HANDLING, AND REPACKING OF MOISTURE-SENSITIVE COMPONENTS - SUPERSEDED BY J-STD-033, May 1999.
Status: RescindedNovember 1999Committee(s): JC-14.4
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JOINT IPC/JEDEC STANDARD FOR HANDLING, PACKING, SHIPPING, AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE-MOUNT DEVICES
The purpose of this document is to provide manufacturers and users with standardized methods for handling, packing, shipping, and use of moisture/reflow and process sensitive devices that have been classified to the levels defined in J-STD-020 or J-STD-075. These methods are provided to avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. By using these procedures, safe and damage-free reflow can be achieved. The dry-packing process defined herein provides a minimum shelf life of 12 months from the seal date.
Committee(s): JC-14, JC-14.1
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CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURES
Status: Reaffirmed September 2019This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures.
Committee(s): JC-14, JC-14.1
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FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.
Committee(s): JC-14.2
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3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies.
Committee(s): JC-14, JC-14.3
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Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress
This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages.
Committee(s): JC-14, JC-14.1
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